Datasheet

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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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15
ANALOG INPUTS
The PCM4204 includes four channels of A/D conversion,
each with its own pair of differential voltage input pins. The
V
IN
1− (pin 1) and V
IN
1+ (pin 2) analog inputs correspond
to Channel 1. The V
IN
2− (pin 58) and V
IN
2+ (pin 59) analog
inputs correspond to Channel 2. The V
IN
3− (pin 54) and
V
IN
3+ (pin 55) analog inputs correspond to Channel 3. The
V
IN
4− (pin 47) and V
IN
4+ (pin 48) analog inputs
correspond to Channel 4. The average input impedance of
each input pin is 3.0kΩ.
Each analog input pair accepts a full-scale input voltage of
approximately 6.0V
PP
differential. The analog input should
not swing below analog ground or above the V
CC
1 (pin 5)
or V
CC
2 (pin 44) power supplies by more than 300mV.
Schottky diodes may be used to clamp these pins to a safe
input range, or the input buffer circuitry may be designed
in a manner to ensure that the input swing does not exceed
the absolute maximum ratings of the PCM4204.
Refer to
the Applications Information section of this datasheet for
an example input buffer circuit.
VOLTAGE REFERENCES AND COMMON MODE
BIAS VOLTAGE OUTPUTS
The PCM4204 includes two on-chip voltage references,
one for Channels 1 and 2 and another for Channels 3 and
4. The V
REF
12− (pin 63) and V
REF
12+ (pin 64) outputs
correspond to low and high reference outputs for Channels
1 and 2. The V
REF
34− (pin 50) and V
REF
34+ (pin 49)
outputs correspond to low and high reference outputs for
Channels 3 and 4. De-coupling capacitors are connected
between the high and low reference pins, and the low
reference pin is then connected to an analog ground. It is
recommended to have at least a 0.1µF X7R ceramic chip
capacitor connected in parallel with a 33µF low ESR
capacitor (tantalum, multilayer ceramic, or aluminum
electrolytic) for de-coupling purposes.
Refer to the Applications Information section of this
datasheet for the recommended voltage reference pin
connections.
The V
REF
12+ and V
REF
34+ outputs should not be utilized
to bias external circuitry, as they are not buffered. Use the
V
COM
12 (pin 16) and V
COM
34 (pin 52) outputs to bias
external circuitry. Although the V
COM
L and V
COM
R outputs
are internally buffered, the output current is limited to a few
hundred µA. It is recommended to connect these pins to
external nodes with greater than 1MΩ impedance, or to
buffer the outputs with a voltage follower circuit when
driving multiple external nodes.
Refer to the Applications Information section of this
datasheet for an example input buffer circuit that utilizes
the common-mode bias voltage outputs.
SYSTEM CLOCK INPUT
The PCM4204 requires a system clock, from which the
modulator oversampling and digital sub-system clocks are
derived. The system clock is applied at the SCKI input (pin
15). The frequency of the system clock is dependent upon
the desired PCM output sampling frequency or DSD data
rate, along with the sampling mode selection. Table 1
shows the corresponding system clock frequencies for
common output sampling and data rates, along with the
corresponding sampling modes. Timing requirements for
the system clock are shown in Figure 2.
Table 1. System Clock Frequencies for Common Output Sampling and Data Rates
SAMPLING FREQUENCY, f
S
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING MODE
SAMPLING FREQUENCY, f
S
(kHz)
128f
S
192f
S
256f
S
384f
S
512f
S
768f
S
Single Rate 32 n/a n/a 8.192 12.288 16.384 24.576
Single Rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688
Single Rate 48 n/a n/a 12.288 18.432 24.576 36.864
Dual Rate 88.2 n/a n/a 22.5792 33.8688 n/a n/a
Dual Rate 96 n/a n/a 24.576 36.864 n/a n/a
Quad Rate 176.4 22.5792 33.8688 n/a n/a n/a n/a
Quad Rate 192 24.576 36.864 n/a n/a n/a n/a
DSD Input/Output 128f
S
Data (Single Rate) n/a n/a 11.2896 16.9344 22.5792 33.8688
DSD Input/Output 64f
S
Data (Dual Rate) n/a n/a 11.2896 16.9344 n/a n/a