Datasheet

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SBAS290B − JULY 2003 − SEPTEMBER 2004
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18
RESET OPERATION
The PCM4202 includes two reset functions: power-on and
externally controlled. This section describes the operation
of each of these functions.
On power-up, the internal reset signal is forced low, forcing
the PCM4202 into a reset state. The power-on reset circuit
monitors the V
DD
(pin 14) and V
CC
(pin 22) power supplies.
When the V
DD
supply exceeds +2.0V (±400mV) and the
V
CC
supply exceeds +4.0V (±400mV), the internal reset
signal is forced high. The PCM4202 then waits for the
system clock input (SCKI) to become active. Once the
system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pins are
forced low. Once the initialization sequence is completed,
the PCM4202 output is enabled. Figure 8 shows the
power-on reset sequence timing.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST
input (pin 19). The RST input is active low, and
requires a minimum low pulse width of 40ns. The
low-to-high transition of the applied reset signal forces an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 9 illustrates
the reset sequence initiated when using the RST
input.
Figure 10 shows the state of the audio data outputs for the
PCM4202 before, during and after the reset operations.
1024 System Clock Periods
Required for Initialization
System Clock
Indeterminate
or Inactive
SCKI
~2.0V
~4.0V
0V
0V
0V
0V
Internal
Reset
V
CC
V
DD
Figure 8. Power-On Reset Sequence