Datasheet

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SBAS342B − DECEMBER 2004 − REVISED APRIL 2006
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15
POWER-DOWN OPERATION
The PCM4201 can be forced to a power-down state by
applying a low level to the RST
input (pin 7) for a minimum
of 65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and the output data pin is
forced low. The system clock may then be removed to
conserve additional power. Before exiting power-down
mode, the system and audio clocks should be restarted.
Once the clocks are active, the RST
input may be driven
high, which initiates a reset initialization sequence.
Figure 10 illustrates the state of the output data pins
before, during, and upon exiting the power-down state.
Valid Output Data Valid Output Data
Outputs
Forced Low
Outputs
Forced Low
Outputs
Forced Low
Enter
Power−Down
State
1024 SCKI Periods
Required for Initialization
65,536
SCKI Periods
RST
Output
Data Pins
HI
LO
Figure 10. ADC Digital Output State for Power-Down Operation