Datasheet

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SBAS342B − DECEMBER 2004 − REVISED APRIL 2006
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11
ANALOG INPUTS
The PCM4201 features differential voltage inputs. V
IN
+
(pin 1) and V
IN
− (pin 2) provide the noninverting and
inverting inputs, respectively. The full-scale input voltage,
measured differentially across these two pins, is
approximately 5.0V
PP
. The input impedance is
approximately 15kΩ per input pin.
In applications where the analog inputs can be driven
beyond the analog supply rails of the PCM4201, the input
buffer circuit should incorporate clamping or limiting
circuitry to ensure that the analog inputs are not driven
beyond the absolute maximum input levels for these pins.
Refer to the Absolute Maximum Ratings table of this
datasheet.
VOLTAGE REFERENCE
The PCM4201 includes an on-chip band gap reference for
the delta-sigma modulator, eliminating the need for
external reference circuitry. The reference voltage is set to
+2.5V nominal. The V
REF
+ (pin 16) and V
REF
− (pin 15)
outputs provide connections for reference decoupling
capacitors, which are connected between these two pins.
The V
REF
− output is then connected to analog ground.
Figure 2 shows the recommended decoupling capacitor
connections and values.
+
PCM4201
10
µ
F
AGND
V
REF
+
V
REF
−
16
15
0.1
µ
F
Figure 2. Voltage Reference Connections
The voltage reference output is not buffered, and should
not be connected to external circuitry other than the
decoupling capacitors. DC common-mode voltage for the
input buffer circuitry may be set using an external voltage
divider circuit, as shown in the Applications Information
section of this datasheet.
SYSTEM CLOCK
The PCM4201 requires an external system clock, which is
used internally to derive the modulator oversampling and
digital subsystem clocks. The system clock is input at
SCKI (pin 12). The acceptable system clock frequency
and duty cycle range are listed in the Electrical
Characteristics table of this datasheet.
The PCM4201 supports specific system clock rates, which
are multiples of the desired output sampling frequency.
The supported system clock rate is also dependent upon
the audio serial port mode. Table 1 and Table 2 specify the
system clock rates required for common output sampling
frequencies for both Slave and Master mode audio
serial-port operation.
Table 1. System Clock Rates for Common Audio
Sampling Frequencies—Slave Mode Operation
SAMPLING
SAMPLING
FREQUENCY
SYSTEM CLOCK
FREQUENCY (MHZ)
SAMPLING
MODE
FREQUENCY
(kHz)
SCKI = 256f
S
SCKI = 512f
S
Normal 32 8.192 16.384
Normal 44.1 11.2896 22.5792
Normal 48 12.288 24.576
Double 88.2 22.5792 N/A
Double 96 24.576 N/A
Table 2. System Clock Rates for Common Audio
Sampling Frequencies—Master Mode Operation
SAMPLING
SAMPLING
FREQUENCY
SYSTEM CLOCK
FREQUENCY (MHZ)
SAMPLING
MODE
FREQUENCY
(kHz)
SCKI = 256f
S
SCKI = 512f
S
Normal 32 N/A 16.384
Normal 44.1 N/A 22.5792
Normal 48 N/A 24.576
Double 88.2 22.5792 N/A
Double 96 24.576 N/A
SAMPLING MODES
The PCM4201 supports three sampling modes, allowing the
user to select the most appropriate power/performance
combination for a given application. The following
paragraphs describe the operation and tradeoffs for the three
sampling modes. For all cases, f
S
is defined as the desired
output sampling rate at the audio serial port interface.
Normal Speed, Low Power mode provides the lowest
overall power dissipation, while supporting sampling rates
up to 54kHz. The modulator oversampling rate is 64f
S
for
this mode, which results in lower dynamic range and
THD+N when compared to Normal Speed, High
Performance mode. For best dynamic performance and
lowest power consumption when using Low Power mode,
it is recommended to operate the PCM4201 from a +1.8V
digital power supply.