Datasheet

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

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BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)

RST 0 0 0 PDN34 PDN12 FS1 FS0

This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft

reset.

FS[1:0] Sampling Mode

FS1 FS0 Sampling Mode

0 0 Single Rate (default)

0 1 Dual Rate

1 0 Quad Rate

1 1 − Not Used −

PDN12 Power-Down for Channels 1 and 2

PDN12 Power Down for Channels 1 and 2

0 Disabled (default)

1 Enabled

PDN34 Power Down for Channels 3 and 4

0 Disabled (default)

1 Enabled

RST Software Reset (value defaults to 0)

Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset

applied at the RST

input (pin 9).

BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)

0 0 BCKE LRCKP 0 FMT2 FMT1 FMT0

This register is used to control the data format and clock polarity for the PCM4104 audio serial port.

FMT[2:0] Audio Data Format

FMT2 FMT1 DEM0 Data Format

0 0 0 24-bit left justified (default)

0 0 1 24-bit I

0 1 0 TDM with zero BCK delay

0 1 1 TDM with one BCK delay

1 0 0 24-bit right justified

1 0 1 20-bit right justified

1 1 0 18-bit right justified

1 1 1 16-bit right justified

LRCKP LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0.

BCKE BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.