Datasheet

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
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21
System Clock
SUB
SUB
PCM4104
PCM4104
Device #1
(Sub−Frame 0)
Device #2
(Sub−Frame 1)
SCKI
V
CC
FSX
CLKX
DX
LRCK
BCK
DATA0
LRCK
BCK
DATA0
DSP
SCKI
Figure 12. TDM Connection
LRCK
Normal, Zero BCK Delay
LRCK
Normal, One BCK Delay
LRCK
Inverted, Zero BCK Delay
LRCK
Inverted, One BCK Delay
DATA0
Supports 8 Channels, or
two PCM4104 devices.
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8
Ch.1 Ch.2 Ch.3 Ch.4 Ch.1 Ch.2 Ch.3 Ch.4
Sub−Frame 0
(SUB = 0)
Sub−Frame 1
(SUB = 1)
One Frame
BCK = 192f
S
or 256f
S
In the case of BCK = 192f
S
, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.
In the case of BCK = 256f
S
, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’tcarebits.
Audio data is always presented in two’s complement, MSB−first format.
TDM Data Formats
−
Long Frame
Supported for Single and Dual Rate Sampling Modes Only
Figure 13. TDM Data Formats: Long Frame