Datasheet

REGISTER DEFINITIONS
PCM3168A
PCM3168A-Q1
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
64 40 MRST SRST — — — — SRDA1 SRDA0
MRST Mode control register reset for the ADC and DAC
This bit sets the mode control register reset to the default value. Pop-noise may be generated.
Returning the MRST bit to '1' is unneccesary, because it is automatically set to '1' after the mode
control register is reset.
Default value = 1.
MRST Mode control register reset
0 Set default value
1 Normal operation (default)
SRST System reset for the ADC and DAC
This bit controls system reset, the relation between system clock and sampling clock
re-synchronization, and ADC operation and DAC operation restart. The mode control register is
not reset and the PCM3168A and PCM3168A-Q1 do not go into a power-down state. The fade-in
sequence is supported in the resume process, but pop-noise may be generated. Returning the
SRST bit to '1' is unneccesary; it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST System reset
0 Resynchronization
1 Normal operation (default)
SRDA[1:0] DAC Sampling mode select
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is
automatically set according to multiples between the system clock and sampling clock, single rate
for 512 f
S
and 768 f
S
, dual rate for 256 f
S
or 384 f
S
, and quad rate for 128 f
S
and 192 f
S
.
Default value = 00.
SRDA DAC Sampling mode select
00 Auto (default)
01 Single rate
10 Dual rate
11 Quad rate
38 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1