Datasheet

LRCKDA
(Slave)
BCKDA
Left-JustifiedMode
DIN1
(Dual)
I SMode
2
DIN1
(Dual)
Left-JustifiedMode
DIN1/2
(Quad)
I SMode
2
DIN1/2
(Quad)
1/f (256BCKsatDualRate,128BCKsatQuadRate)
S
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 220
23 22 1 0 23 22 1 0 23 22 1 0 23 22 23 221 0
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 220
23 22 1 0 1 0 1 023 22 23 22 1 023 22 23 22
Ch1
32BCKs
Ch2
32BCKs
Ch3
32BCKs
Ch4
32BCKs
Ch5
32BCKs
Ch6
32BCKs
Ch7
32BCKs
Ch8
32BCKs
Ch1/Ch5
32BCKs
Ch2/Ch6
32BCKs
Ch3/Ch7
32BCKs
Ch4/Ch8
32BCKs
AUDIO INTERFACE TIMING
BCKAD/DA
(Input)
1.4V
1.4V
1.4V
0.5 VDD´
t
LRS
t
DOD
LRCKAD/DA
(Input)
DOUT1/2/3
DIN1/2/3/4
t
DIH
t
LRH
t
DIS
t
BCH
t
BCL
t
BCY
PCM3168A
PCM3168A-Q1
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
Figure 41. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 f
S
, 256 f
S
, DAC, and Slave Mode Only)
Figure 42 through Figure 45 describe the detailed interface timing specifications.
Figure 42. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I
2
S Data Formats
(Slave Mode)
Table 9. Timing Requirements for Figure 42
(1)
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
BCY
BCKAD/DA cycle time 75 ns
t
BCH
BCKAD/DA pulse width high 35 ns
t
BCL
BCKAD/DA pulse width low 35 ns
t
LRS
LRCKAD/DA setup time to BCKAD/DA rising edge 10 ns
t
LRH
LRCKAD/DA hold time to BCKAD/DA rising edge 10 ns
t
DIS
DIN1/2/3/4 setup time to BCKDA rising edge 10 ns
t
DIH
DIN1/2/3/4 hold time to BCKDA rising edge 10 ns
t
DOD
DOUT1/2/3 delay time from BCKAD falling edge 0 30 ns
(1) Load capacitance of output is 20 pF.
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