Datasheet
PCM3168A
PCM3168A-Q1
www.ti.com
......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued)
All specifications at T
A
= +25 ° C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, f
S
= 48 kHz,
SCKI = 512 f
S
, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless
otherwise noted.
PCM3168A, PCM3168A-Q1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT
1.6 ×
Output voltage Differential V
PP
VCCDA1
0.5 ×
Center voltage V
VCCDA1
To ac-coupled GND
(3)
5 k Ω
Load impedance
To dc-coupled GND
(3)
15 k Ω
f = 20 kHz – 0.04 dB
Low-pass filter frequency response
f = 44 kHz – 0.18 dB
DIGITAL FILTER PERFORMANCE
(4)
Sharp roll-off
Passband (single, dual) 0.454 × f
S
Hz
Passband (quad) 0.432 × f
S
Hz
Stop band (single, dual) 0.546 × f
S
Hz
Stop band (quad) 0.569 × f
S
Hz
Passband ripple < 0.454 × f
S
, 0.432 × f
S
± 0.0018 dB
Stop band attenuation > 0.546 × f
S
, 0.569 × f
S
– 75 dB
DIGITAL FILTER PERFORMANCE Slow roll-off
Passband 0.328 × f
S
Hz
Stop band 0.673 × f
S
Hz
Passband ripple < 0.328 × f
S
± 0.0013 dB
Stop band attenuation > 0.673 × f
S
– 75 dB
DIGITAL FILTER PERFORMANCE
(4)
Group delay time (single, dual) 28/f
S
sec
Group delay time (quad) 19/f
S
sec
De-emphasis error ± 0.1 dB
POWER-SUPPLY REQUIREMENTS
VCCxx1/2 4.5 5.0 5.5 VDC
Voltage range
VDD1/2 3.0 3.3 3.6 VDC
f
S
= 48 kHz/ADC, f
S
= 48 kHz/DAC 162 210 mA
I
CC
f
S
= 96 kHz/ADC, f
S
= 192 kHz/DAC 162 mA
Full power-down
(5)
300 µ A
Supply current
f
S
= 48 kHz/ADC, f
S
= 48 kHz/DAC 106 130 mA
I
DD
f
S
= 96 kHz/ADC, f
S
= 192 kHz/DAC 127 mA
Full power-down
(5)
50 µ A
f
S
= 48 kHz/ADC, f
S
= 48 kHz/DAC 1160 1480 mW
f
S
= 96 kHz/ADC, f
S
= 192 kHz/DAC 1230 mW
Power dissipation f
S
= 48 kHz/ADC, Power-down/DAC 660 mW
Power-down/ADC, f
S
= 48 kHz/DAC 633 mW
Full power-down
(5)
1.67 mW
(3) Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k
for ac-coupled and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection, refer to Figure 62 and Figure 63 of the Application Information
section.
(4) Exclude single and dual at 128 f
S
, 192 f
S
system clock and quad at 256 f
S
to 768 f
S
system clock, and specifications for quad, single,
and dual are respectively applied in reverse for them.
(5) Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA.
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