Datasheet
TIMING CHARACTERISTICS: FOUR-WIRE
MS
1.4V
1.4V
1.4V
0.5 ´ VDD
t
MSH
t
MDD
t
MDR
LSB(D0)
LSB(D0)
Hi-Z
t
MSS
t
MCH
t
MCL
t
MDD
t
MDS
ADR0
MSB(R/ )W
MSB(D7)
Hi-Z
MC
MDI
MDO
t
MDH
t
MCY
t
MHH
MSB(D7)
TWO-WIRE (I
2
C) SERIAL CONTROL
MSB LSB
1
0 0 0
1
ADR1
ADR0
R/W
PCM3168A
PCM3168A-Q1
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......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
(1) These timing parameters are critical for proper control port operation.
Figure 50. Four-Wire Serial Control Interface Timing
(1)
Timing Requirements for Figure 50
(1)
PCM3168A, PCM3168A-Q1
SYMBOL PARAMETER MIN MAX UNIT
t
MCY
MC pulse cycle time 100 ns
t
MCL
MC low-level time 40 ns
t
MCH
MC high-level time 40 ns
t
MHH
MS high-level time t
MCY
ns
t
MSS
MS falling edge to MC rising edge 30 ns
t
MSH
MS rising edge from MC rising edge for LSB 15 ns
t
MDH
MDI hold time 15 ns
t
MDS
MDI setup time 15 ns
t
MDD
MDO enable or delay time from MC falling edge 0 30 ns
t
MDR
MDO disable time from MS rising edge 0 30 ns
(1) These timing parameters are critical for proper control port operation.
The PCM3168A and PCM3168A-Q1 support an I
2
C-compatible serial bus and data transmission protocol for fast
mode configured as a slave device. This protocol is explained in the I
2
C specification, version 2.0.
The PCM3168A and PCM3168A-Q1 have a 7-bit slave address, as shown in Figure 51 . The first five bits are the
most significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the
address byte are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four
PCM3168A and PCM3168A-Q1s can be connected on the same bus at any one time. Each PCM3168A and
PCM3168A-Q1 respond when it receives its own slave address.
Figure 51. Slave Address
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Product Folder Link(s): PCM3168A PCM3168A-Q1