Datasheet

FOUR-WIRE (SPI) SERIAL CONTROL
CONTROL DATA WORD FORMAT
ADR6
R/
W
RegisterAddress RegisterData
ADR5
ADR4
ADR3
ADR2 ADR1
ADR0
D7
D6 D5
D4
D3
D2 D1
D0
MSB LSB
PCM3168A
PCM3168A-Q1
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The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in
hardware control mode, as shown in Table 13 . The software mode provides full selections of 32 kHz, 44.1 kHz,
and 48 kHz.
Table 13. Hardware Control Mode
DEMP (DE-EMPHASIS FILTER ENABLE) DESCRIPTION
Low 44.1 kHz, de-emphasis disabled
High 44.1 kHz, de-emphasis enabled
The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The
selectable multiple of the master mode audio interface is limited between 256 f
S
, 384 f
S
, and 512 f
S
; the
selectable sampling mode is limited as shown in Table 14 . The software mode provides full selections.
Table 14. Selectable Sampling Mode
DESCRIPTION
INTERFACE MODE SAMPLING MODE
MD1 MD0 ADC DAC ADC DAC
Low Low Slave
(1)
Slave
(1)
Auto
(2)
Auto
(2)
Low High Master, 512 f
S
Slave
(1)
Single rate Auto
(2)
High Low Master, 384 f
S
Slave
(1)
Dual rate Auto
(2)
High High Master, 256 f
S
Slave
(1)
Dual rate Auto
(2)
(1) The multiples between system clock and sampling frequency are automatically detected; 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
are
acceptable for ADC operation, and 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
are acceptable for DAC operation.
(2) The sampling mode is automatically set as single rate for 512 f
S
and 768 f
S
, dual rate for 256 f
S
and 384 f
S
, and quad rate for 128 f
S
and
198 f
S
, according to the detected multiples between the system clock and sampling clock.
The PCM3168A and PCM3168A-Q1 include an SPI-compatible serial port that operates asynchronously with the
audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and
MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output
to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is
the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.
All single write/read operations via the serial control port use 16-bit data words. Figure 47 shows the control data
word format. The first bit is for read/write controls; '0' indicates a write operation and '1' indicates a read
operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the
write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written
to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].
Figure 47. Control Data Word Format for MDI
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