Datasheet
BCKAD/DA
(Output)
LRCKAD/DA
(Output)
DOUT1/2/3
DIN1/2/3/4
t
DOD
t
LRD
1.4V
0.5 VDD´
0.5 VDD´
0.5 VDD´
t
BCH
t
BCL
t
BCY
t
DIS
t
DIH
t
LRW
PCM3168A
PCM3168A-Q1
SBAS452 – SEPTEMBER 2008 .........................................................................................................................................................................................
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Timing Requirements for Figure 44
(1)
SYMBOL DESCRIPTION MIN TYP MAX UNIT
BCKAD cycle time 75 ns
t
BCY
BCKDA cycle time 40 ns
BCKAD pulse width high 35 ns
t
BCH
BCKDA pulse width high 15 ns
BCKAD pulse width low 35 ns
t
BCL
BCKDA pulse width low 15 ns
LRCKAD/DA pulse width high (DSP format) t
BCY
t
LRW
LRCKAD/DA pulse width high (TDM format) t
BCY
1/f
S
– t
BCY
t
LRS
LRCKAD/DA setup time to BCKAD/DA rising edge 10 ns
t
LRH
LRCKAD/DA hold time to BCKAD/DA rising edge 10 ns
t
DIS
DIN1/2/3/4 setup time to BCKDA rising edge 10 ns
t
DIH
DIN1/2/3/4 hold time to BCKDA rising edge 10 ns
t
DOD
DOUT1/2/3 delay time from BCKAD falling edge 0 30 ns
(1) Load capacitance of output is 20 pF.
Figure 45. Audio Interface Timing Requirements for DSP and TDM Data Formats (Master Mode)
Timing Requirements for Figure 45
(1)
SYMBOL DESCRIPTION MIN TYP MAX UNIT
BCKAD/DA cycle time (DSP format) 1/(64 f
S
)
t
BCY
BCKAD/DA cycle time (TDM format, single rate) 1/(256 f
S
)
BCKAD/DA cycle time (TDM format, dual rate) 1/(128 f
S
)
t
BCH
BCKAD/DA pulse width high 0.4 t
BCY
0.5 t
BCY
0.6 t
BCY
t
BCL
BCKAD/DA pulse width low 0.4 t
BCY
0.5 t
BCY
0.6 t
BCY
LRCKAD/DA pulse width high (DSP format) t
BCY
t
LRW
LRCKAD/DA pulse width high (TDM format) 1/(2 f
S
)
t
LRD
LRCKAD/DA delay time from BCKAD/DA falling edge – 10 20 ns
t
DIS
DIN1/2/3/4 setup time to BCKDA rising edge 10 ns
t
DIH
DIN1/2/3/4 hold time to BCKDA rising edge 10 ns
t
DOD
DOUT1/2/3 delay time from BCKAD falling edge – 10 20 ns
(1) Load capacitance of output is 20 pF.
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