PCM3168A PCM3168A-Q1 Burr-Brown Audio www.ti.com .........................................................................................................................................................................................
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DESCRIPTION The PCM3168A and PCM3168A-Q1 are high-performance, single-chip, 24-bit, 6-in/8-out, audio coders/decoders (codecs) with single-ended and differential selectable analog inputs and differential outputs.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). PCM3168A, PCM3168A-Q1 UNIT Supply voltage: VCCAD1, VCCAD2, VCCDA1, VCCDA2 –0.3 to +6.5 V Supply voltage: VDD1, VDD2 –0.3 to +4.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: Digital Input/Output All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: ADC Characteristics All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: ADC Characteristics (continued) All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued) All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued) All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 www.ti.com .........................................................................................................................................................................................
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.
PCM3168A PCM3168A-Q1 www.ti.com .........................................................................................................................................................................................
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS ADC Digital Filter All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DAC Digital Filter All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DAC Digital Filter (continued) All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 ADC Performance All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DAC Performance All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 Output Spectrum All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Power-Supply All specifications at TA = +25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 PRODUCT OVERVIEW The PCM3168A and PCM3168A-Q1 are high-performance, multi-channel codecs targeted for automotive audio applications such as external amplifiers, as well as home multi-channel audio applications (for example, home theaters and A/V receivers).
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com VOLTAGE REFERENCES The PCM3168A and PCM3168A-Q1 include two internal references for the six-channel ADCs; these references correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog ground via decoupling capacitors.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com RESET OPERATION The PCM3168A and PCM3168A-Q1 have both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are illustrated in Figure 33, Table 7, and Figure 34.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 (VDD = 3.3 V, typ) VDD SCKI, BCKAD/DA, LRCKAD/DA 0V Synchronous Clocks Synchronous Clocks 100 ns (min) RST 3846 ´ SCKI Internal Reset Normal Operation Power-Down Normal Operation tDACDLY2 tDACDLY1 VOUT1± to VOUT8± 0.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Table 8.
PCM3168A PCM3168A-Q1 www.ti.com .........................................................................................................................................................................................
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 tBCH tBCL BCKAD/DA (Output) 0.5 ´ VDD tBCY tLRD LRCKAD/DA (Output) 0.5 ´ VDD tDOD DOUT1/2/3 0.5 ´ VDD tDIS tDIH DIN1/2/3/4 1.4 V Figure 43.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM The PCM3168A and PCM3168A-Q1 operate under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA). Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com OVERFLOW FLAG The PCM3168A and PCM3168A-Q1 include an overflow flag output for all ADC channels. As soon as any of the six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in hardware control mode, as shown in Table 13. The software mode provides full selections of 32 kHz, 44.1 kHz, and 48 kHz. Table 13.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com REGISTER WRITE OPERATION Figure 48 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register must be written. To start the register write cycle, MS is set to a low state.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 TIMING CHARACTERISTICS: FOUR-WIRE tMHH MS 1.4 V tMCH tMSS tMCL tMSH MC 1.4 V tMCY tMDS MDI tMDH MSB (D7) ADR0 MSB (R/W) LSB (D0) 1.4 V tMDD Hi-Z MDO tMDR tMDD MSB (D7) LSB (D0) Hi-Z 0.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com PACKET PROTOCOL A master device must control the packet protocol, which consists of the start condition, slave address with the read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop condition.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 TIMING REQUIREMENTS: SCL AND SDA Repeated START START tBUF STOP tD-HD tD-SU tSDA-R tP-SU SDA tSCL-R tSDA-F tS-HD tLOW SCL tSCL-F tS-HD tHI tS-SU Figure 55.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY) The PCM3168A and PCM3168A-Q1 have many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I2C serial control port.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 Table 16.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com REGISTER DEFINITIONS DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 64 40 MRST SRST — — — — SRDA1 SRDA0 MRST Mode control register reset for the ADC and DAC This bit sets the mode control register reset to the default value. Pop-noise may be generated.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 65 41 PSMDA MSDA2 MSDA1 MSDA0 FMTDA3 FMTDA2 FMTDA1 FMTDA0 PSMDA DAC Power-save mode select This bit selects the power-save mode for the OPEDA[3:0] function.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 66 42 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0 OPEDA[3:0] DAC Operation control These bits control the DAC operation mode.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 67 43 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1 REVDA[8:1] DAC Output phase select The REVDA[8:1] bits are used to control the phase of DAC analog signal outputs. Default value: 0000 0000.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 68 44 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1 MUTDA[8:1] DAC Soft Mute control These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 69 45 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 ZERO[8:1] DAC Zero flag (read-only) These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 70 46 ATMDDA ATSPDA DEMP1 DEMP0 AZRO2 AZRO1 AZRO0 ZREV ATMDDA DAC Attenuation mode This bit controls the DAC attenuation mode.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 ZREV DAC Zero flag polarity select This bit controls the polarity of the zero flag pin. Default value: 0.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ATDAx Decimal value Attenuation level setting 1111 1111 255 0 dB, no attenuation (default) 1111 1110 254 –0.5 dB 1111 1101 253 –1.0 dB ... ... 1000 0001 129 –63.0 dB 1000 0000 128 –63.5 dB 0111 1111 127 –64 dB ... ... ... 0011 1000 56 –99.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 81 51 — MSAD2 MSAD1 MSAD0 — FMTAD2 FMTAD1 FMTAD0 MSAD[2:0] ADC Master/slave mode select These bits control the audio interface mode for ADC operation. Default value: 000 (slave mode).
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 82 52 — PSVAD2 PSVAD1 PSVAD0 — BYP2 BYP1 BYP0 PSVAD[2:0] ADC Power-save control These bits control the ADC power-save mode.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 83 53 — — SEAD6 SEAD5 SEAD4 SEAD3 SEAD2 SEAD1 SEAD[6:1] ADC Input configuration control These bits control the input configuration of each ADC channel, differential or single-ended.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 84 54 — — REVAD6 REVAD5 REVAD4 REVAD3 REVAD2 REVAD1 REVAD[6:1] ADC Input phase select These bits are used to control the phase of analog signal inputs. Default value: 00 0000.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 85 55 — — MUTAD6 MUTAD5 MUTAD4 MUTAD3 MUTAD2 MUTAD1 MUTAD[6:1] ADC Soft Mute control These bits are used to enable or disable the Soft Mute function for the corresponding ADC outputs, DOUT.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 86 56 — — OVF6 OVF5 OVF4 OVF3 OVF2 OVF1 OVF[6:1] ADC Overflow flag (read-only) These bits indicate the status information of an overflow detect circuit for each ADC channel; these bits are read only.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 87 57 ATMDAD ATSPAD — — — — — OVFP ATMDAD ADC Attenuation mode This bit controls the ADC attenuation mode.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ATADx[7:0] ADC Digital attenuation level setting Where x = 0 and 1 to 6, corresponding to the ADC channel, ADCx (x = 1 to 6). Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level can be set from 20 dB to –100 dB in 0.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 APPLICATION INFORMATION A typical circuit connection for six-channel analog in and eight-channel analog out is shown in Figure 56.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Typical interface circuits for analog input and analog output are shown in Figure 58 through Figure 63. VIN(1 VRMS) C1 R1 1 mF VIN+ (1 VRMS) + Analog Input+ (1 VRMS) R1 1 mF + Analog Input(1 VRMS) R1 = 47-Ω to 470-Ω resistor, C1 = 0.01-pF to 0.
PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 R2 22 pF R3 VIN+ (1 VRMS) R2 R2 C2 C1 10 mF R1 + Analog Input (2 VRMS) R3 VIN(1 VRMS) VCOMAD 0.1 mF Amplifier is an NE5532A x1 or OPA2134 x1; R1 = 3-kΩ resistor; R2 = 1.5-kΩ resistor; R3 = 47-Ω resistor; C1 = 2200-pF capacitor; C2 = 0.
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com R2 C2 R1 R3 47W C1 + VOUT+ (4 VPP) 10 mF + VOUT(4 VPP) 10 mF R1 Analog Output (2 VRMS) R3 R2 C2 Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 7.5-kΩ resistor; R2 = 5.
PCM3168A PCM3168A-Q1 www.ti.com .........................................................................................................................................................................................
PCM3168A PCM3168A-Q1 SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com MODE Pin This pin is a logic input with quad-state input capability.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 20-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM3168ATPAPRQ1 Package Package Pins Type Drawing HTQFP PAP 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 20-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3168ATPAPRQ1 HTQFP PAP 64 1000 367.0 367.0 45.
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