Datasheet
PCM3070
SLAS724 – FEBRUARY 2011
www.ti.com
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
AVdd to AVss –0.3 to 2.2 V
DVdd to DVss –0.3 to 2.2 V
IOVDD to IOVSS –0.3 to 3.9 V
LDOIN to AVss –0.3 to 3.9 V
Digital Input voltage to IOVDD + 0.3 V
Analog input voltage to AVdd + 0.3 V
Operating temperature range –40 to 85 °C
Storage temperature range °C
Junction temperature (T
J
Max) 105 °C
QFN package (RHB) Power dissipation (T
J
Max – TA)/ θ
JA
W
θ
JA
Thermal impedance 35 C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM MAX UNIT
LDOIN Power Supply Voltage Range Referenced to AVss
(1)
1.9 V
AVdd 1.5 1.8 1.95
IOVDD Referenced to IOVSS
(1)
1.5 3.6
DVdd
(2)
Referenced to DVss
(1)
1.8 1.95
PLL Input Frequency Clock divider uses fractional divide 10 20 MHz
(D > 0), P=1, D
Vdd
≥ 1.65V
Clock divider uses integer divide 0.512 20 MHz
(D = 0), P=1, D
Vdd
≥ 1.65V
MCLK Master Clock Frequency MCLK; Master Clock Frequency; D
Vdd
≥ 1.65V 50 MHz
MCLK; Master Clock Frequency; D
Vdd
≥ 1.26V 25
SCL SCL Clock Frequency 400 kHz
C
Lout
Digital output load capacitance 10 pF
TOPR Operating Temperature Range –40 85 °C
(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground
signals.
(2) At DVdd values lower than 1.65V, the PLL does not function. Please see the Maximum PCM3070 Clock Frequencies table in the
PCM3070 Application Reference Guide (SLAU332) for details on maximum clock frequencies.
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