Datasheet

PCM3070
www.ti.com SLAS724 – FEBRUARY 2011
The PCM3070 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a hi-Z
(3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with the
ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the PCM3070, these clocks are active only
when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However, it
also supports a feature when both the word clocks and bit-clocks can be active even when the codec in the
device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or
when word-clock or bit-clocks are used in the system as general-purpose clocks.
Clock Generation and PLL
The PCM3070 supports a wide range of options for generating clocks for the ADC and DAC sections as well as
interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This clock can
be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then be routed
through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP
sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference clocks
on MCLK BCLK or GPIO, the PCM3070 also provides the option of using the on-chip PLL which supports a wide
range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the
PCM3070 provides several programmable clock dividers to help achieve a variety of sampling rates for ADC,
DAC and clocks for the miniDSP .
For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
Control Interfaces
The PCM3070 control interface supports SPI or I
2
C communication protocols, with the protocol selectable using
the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I
2
C, SPI_SELECT should be tied low. It is
not recommended to change the state of SPI_SELECT during device operation.
I
2
C Control
The PCM3070 supports the I
2
C control protocol, and will respond to the I
2
C address of 0011000. I
2
C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I
2
C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
SPI Control
In the SPI control mode, the PCM3070 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
PCM3070) depend on a master to start and synchronize transmissions. A transmission begins when initiated by
an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the
master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin
to the master shift register.
For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
Power Supply
To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IO
VDD
voltage can be in the range of
1.1V - 3.6V. Internal LDOs generate the appropriate digital core voltage of 1.65V and analog core voltage of 1.8V
(minimum 1.5V). For maximum flexibility, the respective voltages can also be supplied externally, bypassing the
built-in LDOs. To support high-output drive capabilities, the output stages of the output amplifiers can either be
driven from the analog core voltage or the 1.9…3.6V rail used for the LDO inputs (LDO_in).
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Product Folder Link(s): PCM3070