Datasheet

PCM3070
SLAS724 – FEBRUARY 2011 www.ti.com
Table 10. Overview – DAC Predefined Processing Blocks (continued)
Processing Interpolation Channel 1st Order Num. of DRC 3D Beep Resource
Block No. Filter IIR Available Biquads Generator Class
PRB_P3 A Stereo Yes 6 No No No 10
PRB_P4 A Left No 3 No No No 4
PRB_P5 A Left Yes 6 Yes No No 6
PRB_P6 A Left Yes 6 No No No 6
PRB_P7 B Stereo Yes 0 No No No 6
PRB_P8 B Stereo No 4 Yes No No 8
PRB_P9 B Stereo No 4 No No No 8
PRB_P10 B Stereo Yes 6 Yes No No 10
PRB_P11 B Stereo Yes 6 No No No 8
PRB_P12 B Left Yes 0 No No No 3
PRB_P13 B Left No 4 Yes No No 4
PRB_P14 B Left No 4 No No No 4
PRB_P15 B Left Yes 6 Yes No No 6
PRB_P16 B Left Yes 6 No No No 4
PRB_P17 C Stereo Yes 0 No No No 3
PRB_P18 C Stereo Yes 4 Yes No No 6
PRB_P19 C Stereo Yes 4 No No No 4
PRB_P20 C Left Yes 0 No No No 2
PRB_P21 C Left Yes 4 Yes No No 3
PRB_P22 C Left Yes 4 No No No 2
PRB_P23 A Stereo No 2 No Yes No 8
PRB_P24 A Stereo Yes 5 Yes Yes No 12
PRB_P25 A Stereo Yes 5 Yes Yes Yes 12
For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
Digital Audio I/O Interface
Audio data is transferred between the host processor and the PCM3070 via the digital audio data serial interface,
or audio bus. The audio bus on this device is very flexible, including left or right-justified data options, support for
I
2
S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a
system directly.
The audio bus of the PCM3070 can be configured for left or right-justified, I
2
S, DSP, or TDM modes of operation,
where communication with standard PCM interfaces is supported within the TDM mode. These modes are all
MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27, D(5:4). In
addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for
flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame,
and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to
the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various
word-lengths as well as to support the case when multiple PCM3070s may share the same audio bus.
The PCM3070 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0,
Register 28.
The PCM3070 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as
compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. This can be configured via Page 0, Register 29, D(3).
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