Datasheet

PCM3070
www.ti.com SLAS724 – FEBRUARY 2011
Electrical Characteristics, Misc.
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, f
s
(Audio) = 48kHz, Cref = 10 μF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
CMMode = 0 (0.9V) 0.9
Reference Voltage Settings V
CMMode = 1 (0.75V) 0.75
Reference Noise CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, 1 μV
RfcMS
C
ref
= 10μF
Decoupling Capacitor 1 10 μF
miniDSP
(1)
Maximum miniDSP clock frequency - ADC DVdd = 1.65V 55.3 MHz
Maximum miniDSP clock frequency - DAC DVdd = 1.65V 55.3 MHz
Shutdown Current
Coarse AVdd supply turned off, LDO_select held at
Device Setup
ground, No external digital input is toggled
I(DVdd) 0.9 μA
I(IOVDD) 13 nA
(1) docato-extra-info-title miniDSP miniDSP Processing-block clock speed is specified by design and not tested in production.
Electrical Characteristics, Logic Levels
At 25°C, AVdd, DVdd, IOVDD = 1.8V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC FAMILY CMOS
V
IH
Logic Level I
IH
= 5 μA, IOVDD > 1.6V 0.7 × IOVDD V
I
IH
= 5μA, 1.2V ≤ IOVDD <1.6V 0.9 × IOVDD V
I
IH
= 5μA, IOVDD < 1.2V IOVDD V
V
IL
I
IL
= 5 μA, IOVDD > 1.6V –0.3 0.3 × IOVDD V
I
IL
= 5μA, 1.2V ≤ IOVDD <1.6V 0.1 × IOVDD V
I
IL
= 5μA, IOVDD < 1.2V 0 V
V
OH
I
OH
= 2 TTL loads 0.8 × IOVDD V
V
OL
I
OL
= 2 TTL loads 0.1 × IOVDD V
Capacitive Load 10 pF
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