Datasheet

www.ti.com
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 72 0 1 0 0 1 0 0 0 CSEL1 M/ S 12 M/ S 11 M/ S 10 RSV RSV FMT11 FMT10
CSEL1: Clock Select for ADC Operation
Default value: 0 (SCKI1, BCK1, LRCK1 enabled for ADC operation)
CSEL1 = 0 SCKI1, BCK1, LRCK1 enabled for ADC operation (default)
CSEL1 = 1 SCKI2, BCK2, LRCK2 enabled for ADC operation
The CSEL1 bit controls the system clock and audio interface clocks for the ADC operation.
SCKI1, BCK1, LRCK1 are used for ADC portion if CSEL1 = 0 (default), and SCKI2, BCK2, LRCK2 are used for
ADC portion if CSEL1 = 1.
M/ S 1[2:0]: Audio Interface Mode for ADC
Default value: 000 (slave mode)
M/ S 1[2:0] Audio Interface Mode for ADC
0 0 0 Slave mode (default)
0 0 1 Master mode, 768 f
S
0 1 0 Master mode, 512 f
S
0 1 1 Master mode, 384 f
S
1 0 0 Master mode, 256 f
S
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
The M/ S 1[2:0] bits control the audio interface mode for the ADC.
FMT1[1:0]: Audio Interface Format for ADC
Default value: 00 (I
2
S mode)
FMT1[1:0] Audio Interface Format for ADC
0 0 24-bit I
2
S format (default)
0 1 24-bit left-justified format
1 0 24-bit right-justified format
1 1 16-bit right-justified format
The FMT1[1:0] bits control the audio interface mode for ADC.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): PCM3060