Datasheet
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Timing Diagram
SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
RepeatedStart
t
(S-SU)
t
(S-HD)
t
(SDA-F)
t
(SDA-R)
t
(P-SU)
Stop
t
(GW)
T0050-04
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
The detailed timing diagram for SCL and SDA is shown as follows.
Timing Characteristics
STANDARD MODE FAST MODE
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
f
(SCL)
SCL clock frequency 100 400 kHz
t
(BUF)
Bus free time between STOP and START conditions 4.7 1.3 µ s
t
(LOW)
Low period of the SCL clock 4.7 1.3 µ s
t
(HI)
High period of the SCL clock 4 0.6 µ s
t
(S-SU)
Setup time for START/repeated START condition 4.7 0.6 µ s
t
(S-HD)
Hold time for START/repeated START condition 4 0.6 µ s
t
(D-SU)
Data setup time 250 100 ns
t
(D-HD)
Data hold time 0 3450 0 900 ns
t
(SCL-R)
Rise time of SCL signal 1000 20 + 0.1 C
B
300 ns
t
(SCL-F)
Fall time of SCL signal 1000 20 + 0.1 C
B
300 ns
t
(SDA-R)
Rise time of SDA signal 1000 20 + 0.1 C
B
300 ns
t
(SDA-F)
Fall time of SDA signal 1000 20 + 0.1 C
B
300 ns
t
(P-SU)
Setup time for STOP condition 4 0.6 µ s
t
(GW)
Allowable glitch width N/A 50 ns
C
B
Capacitive load for SDA and SCL lines 400 100 pF
Noise margin at high level for each connected device (including hysteresis) 0.2 V
DD
0.2 V
DD
V
Noise margin at low level for each connected device (including hysteresis) 0.1 V
DD
0.1 V
DD
V
Hysteresis of Schmitt-trigger input N/A 0.05 V
DD
V
Figure 32. Control Interface Timing for I
2
C
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