Datasheet

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Packet Protocol

SDA

SCL St

1-7

8 1-8 9 1-8 9 9

Slave Address ACK DATA ACK DATA ACK ACK

R/W

R/ :ReadOperationif1;Otherwise,WriteOperationW

ACK: AcknowledgementofaByteif0,not AcknowledgementofaByteif1

DATA:8Bits(Byte)

Stop

Condition

Start

Condition

T0049-06

Write Operation

Transmitter

M M M

M MM M

Data Type

St Slave Address

ACK ACK ACK ACK ACK

WriteData1 WriteData2

Reg Address

M:MasterDeviceS:SlaveDeviceSt:StartCondition :Write ACK: AcknowledgementSp:StopConditionW

R0002-04

S S S S

PCM3060

SLAS533B – MARCH 2007 – REVISED MARCH 2008

The PCM3060 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory

preset to 10 0011. The next bit of the address byte is the device select bit, which can be user-defined by the

ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060

responds when it receives its own slave address.

A master device must control packet protocol, which consists of a start condition, slave address with read/write

bit, data if write or acknowledgment if read, and stop condition. The PCM3060 supports the slave receiver

function.

The PCM3060 supports the receiver function. A master can write to any PCM3060 registers using single or

multiple accesses. The master sends a PCM3060 slave address with a write bit, a register address, and the

data. If multiple access is required, the address is that of the starting register, followed by the data to be

transferred. When the data are received properly, the index register is incremented by 1 automatically. When the

index register reaches 4Ah, the next value is 40h. When undefined registers are accessed, the PCM3060 does

not send an acknowledgment. Figure 31 is a diagram of the write operation. The register address and the write

data are 8-bit in MSB-first format.

Figure 31. Framework for Write Operation

Product Folder Link(s): PCM3060