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Timing Requirements
t
(MCH)
1.4V
1.4V
1.4V
MS
t
(MSS)
t
(MCL)
t
(MHH)
t
(MSH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
LSB
T0013-10
TWO-WIRE (I
2
C) SERIAL CONTROL
Slave Address
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
Figure 30 shows a detailed timing diagram for the 3-wire serial control interface. These timing parameters are
critical for proper control port operation.
SYMBOL PARAMETER MIN MAX UNIT
t
(MCY)
MC cycle time 100 ns
t
w(MCL)
MC low-level time 40 ns
t
w (MCH)
MC high-level time 40 ns
t
(MHH)
MS high-level time t
(MCY)
ns
t
(MSS)
MS falling edge to MC rising edge 15 ns
t
(MSH)
MS rising edge from MC rising edge for LSB
(1)
15 ns
t
(MDH)
MD hold time 15 ns
t
(MDS)
MD setup time 15 ns
(1) MC rise edge for LSB to MS rise edge.
Figure 30. Control Interface Timing for SPI
The PCM3060 supports the I
2
C-compatible serial bus and the data transmission protocol for standard-mode and
fast-mode (C
B
max = 100 pF) as a slave device. This protocol is explained in the well-known I
2
C 2.0
specification.
MSB LSB
1 0 0 0 1 1 ADR R/ W
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