Datasheet

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ANALOG INPUTS TO ADC
ANALOG OUTPUTS FROM DAC
V
COM
OUTPUT
OVERSAMPLING RATE CONTROL
ZERO FLAGS
Zero-Detect Condition
Zero-Flag Outputs
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
The PCM3060 has two independent input channels, V
IN
L and V
IN
R. These are single-ended (unbalanced) inputs,
each capable of 0.6-V
CC
Vpp input with 10-k Ω input resistance, typically.
The PCM3060 has two independent output channels, V
OUT
L and V
OUT
R. These are differential, (balanced)
outputs, each capable of driving 0.8-V
CC
Vpp (1.6-Vpp in differential) typical with a 10-k Ω dc-coupled load. The
internal output amplifiers for V
OUT
L+, V
OUT
L – and V
OUT
R+, V
OUT
R – are biased to V
COM
, described as follows.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM3060 delta-sigma modulators.
The frequency response of this filter is shown in the typical performance curves. This filter is not enough to
attenuate the out-of-band noise to an acceptable level for many applications in general. An external low-pass
filter is used if further out-of-band noise rejection in required.
V
OUT
X+, V
OUT
X – configuration can be changed to single-ended (unbalanced) output via a MODE pin setting or
serial mode control, and V
OUT
X+ is assigned as an output pin in single-ended mode.
One unbuffered common voltage output pin, VCOM (pin 20) is brought out for decoupling purposes. This pin is
internally biased to a dc voltage level of 0.5 V
CC
nominal, and is used as an internal common voltage and
reference voltage for the ADC and DAC. This pin can be used to bias an external circuit, but the load impedance
must be high enough for operation with the output resistance of this pin, which is 12.5 k Ω , typically.
The oversampling rate of ADC of PCM3060 is fixed at 64 f
S
, but the oversampling rate of DAC of PCM3060 is
one of 64 f
S
, 32 f
S
or 16 f
S
, and this is automatically selected by the ratio of system clock frequency and sampling
frequency. And it can be also set to double rate, i.e., one of 128 f
S
, 64 f
S
or 32 f
S
, through serial control.
For each DAC channel, the PCM3060 has a zero-detect circuit that recognizes zero detection when 1024
consecutive zeros have been sampled on DIN.
There are two zero-flag outputs, ZEROL and ZEROR. These pins can be used to operate external mute circuits,
or used as status indicators for a microcontroller, audio signal processor, etc. These pins can be programmed in
following two modes using the serial control port as described in the MODE CONTROL section.
DESCRIPTION
AZRO
ZEROL ZEROR
0 (default) L-ch zero detection R-ch zero detection
1 L-ch and R-ch zero detection L-ch and R-ch zero detection
For zero detection, these pins are set to HIGH (1) by default, but the polarity of the zero-flag outputs can be
inverted through the serial control port.
ZREV DESCRIPTION
0 (default) HIGH for zero detection
1 LOW for zero detection
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Product Folder Link(s): PCM3060