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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
Within2/f
S
t
(DACDLY3)
(22/f )
S
Normal
V
COM
(0.5V )
CC
Undefined
Data
Normal
Synchronous
Asynchronous
Synchronous
DACV X+/–
OUT
StateofSynchronization
NormalZeroNormal
ADCDOUT
Undefined
Data
T0020-08
t
(ADCDLY3)
(32/f )
S
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
As the PCM3060 operates under the system clock (SCKI1/2) and the audio sampling clock (LRCK1/2), SCKI1/2
and LRCK1/2 must have a specific relationship in slave mode. The PCM3060 does not need a specific phase
relationship between audio the interface clocks (LRCK1/2, BCK1/2) and system clock (SCKI1/2), but does
require a frequency synchronization of LRCK1/2, BCK1/2, and SCKI1/2.
If the relationship between SCKI2 and LRCK2 changes more than ± 6 BCK2s (BCK2 = 64 f
S
) or ± 5 BCK2s (BCK2
= 48 f
S
) due to jitter or frequency change, etc., internal operation of DAC halts within 2/f
S
, and analog output is
forced to V
COM
(0.5V
CC
) until resynchronization of SCKI2 to LRCK2 and BCK2 is completed and then t
DACDLY3
passes by.
If the relationship between SCKI1 and LRCK1 changes more than ± 6 BCK1s (BCK1 = 64 f
S
) or ± 5 BCK1s (BCK1
= 48 f
S
) due to jitter, frequency change, etc., internal operation of ADC halts within 2/f
S
, and digital output is
forced into ZERO code until resynchronization of SCKI1 to LRCK1 and BCK1 is completed and then t
ADCDLY3
passes by.
In case of changes less than ± 5 BCK1/2s (BCK1/2 = 64) or ± 4 BCK1/2s (BCK1/2 = 48), resynchronization does
not occur, and previously described analog/digital output control and discontinuity do not occur.
Figure 27 illustrates the DAC analog output and ADC digital output for loss of synchronization.
During undefined data, it may generate some noise in audio signal. Also, the transition of normal to undefined
data and undefined or zero data to normal creates a discontinuity in the data on the analog and digital outputs,
which may generate some noise in the audio signal.
The ADC output, DOUT and DAC outputs, and V
OUT
X hold the previous state if the system clock halts.
Figure 27. DAC Output and ADC Output for Loss of Synchronization
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