Datasheet

www.ti.com
V
DD
0 V
RST
Normal OperationNormal Operation
Power Down
0.5
V
CC
ZERO
DOUT
Fade-inFade-out
MODE
1024 SCKIx
(1)
SCKIx,
BCKx,
LRCKx
ADPSV
DAPSV
Internal
Reset
V L+/–
V R+/–
OUT
OUT
(V =
DD
3.3V typ.)
t
1936/f
(ADCDLY2)
S
t
1936/f
(ADCDLY2)
S
T0098-02
t
2048/f
(DACDLY1)
S
t
1616/f
(DACDLY2)
S
t
1616/f
(DACDLY2)
S
V
COM CC
(0.5 V )
2048/f
S
min.
t
2048/f min.
RST
S
Synchronous Clocks Synchronous Clocks
t
2048/f
(ADCDLY1)
S
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
(1) ADPSV and DAPSV control V
OUT
L/R and DOUT, respectively, with fade-in/out the same as for RST.
Figure 23. DAC Output and ADC Output for External Reset
18 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3060