Datasheet
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POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued)
1024 SCKIx
V
DD
0 V
(V = 2.2 V typ.)
DD
Synchronous Clocks
RST
Normal Operation
Power Down
0.5
V
CC
ZERO
DOUT
Fade-in
MODE
1024 SCKIx
(1)
SCKIx,
BCKx,
LRCKx
ADPSV
DAPSV
Internal
Reset
V L+/–
V R+/–
OUT
OUT
(V =
DD
V
DD
3.3V typ.)
( = 2.7V min.)
t
2048/f
(DACDLY1)
S
t
2048/f
(ADCDLY1)
S
t
1616/f
(DACDLY2)
S
t
1936/f
(ADCDLY2)
S
V
COM CC
(0.5 V )
T0097-02
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
NOTE: Release from the power-save mode is required if the software control mode is selected.
Figure 22. DAC Output and ADC Output for Power-On Reset
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