Datasheet

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DEVICE DESCRIPTION
ASYNCHRONOUS OPERATION
SYSTEM CLOCK
t
w(SCH)
t
w(SCL)
2 V
0.8 V
H
L
T0005-14
t
(SCY)
System Clock
(SCK1,SCK2)
PCM3060
SLAS533B – MARCH 2007 – REVISED MARCH 2008
The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two
independent system clocks on SCKI1 and SCKI2.
Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system
clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register 67 or 72 in serial
mode control.
The PCM3060 requires two system clocks for operating the ADC and DAC blocks independently, or it requires
one common clock for synchronous ADC and DAC operation.
The system clock for the ADC of the PCM3060 must be 256, 384, 512, or 768 f
S
, where f
S
is the audio sampling
rate for the ADC, 16 to 96 kHz.
The system clock for the DAC of the PCM3060 must be 128, 192, 256, 384, 512, or 768 f
S
, where f
S
is the audio
sampling rate for the DAC, 16 to 192 kHz.
Table 2 lists the typical system clock frequencies, f
SCKI1
and f
SCKI2
for common audio sampling rates, and
Figure 21 shows the timing requirements for the system clock inputs.
Table 2. System Clock Frequencies for Common Audio Sampling Clock Frequencies
SAMPLING SYSTEM CLOCK FREQUENCY, f
SCKI1
, f
SCKI2
[MHz]
FREQUENCY
128 f
S
(1)
192 f
S
(1)
256 f
S
384 f
S
512 f
S
768 f
S
(kHz)
16 2.048 3.072 4.096 6.144 8.192 12.288
32 4.096 6.144 8.192 12.288 16.384 24.576
44.1 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688
48 6.144 9.216 12.288 18.432 24.576 36.864
88.2 11.2896 16.9344 22.5792 33.8688 See
(2)
See
(2)
96 12.288 18.432 24.576 36.864 See
(2)
See
(2)
176.4
(1)
22.5792 33.8688 See
(2)
See
(2)
See
(2)
See
(2)
192
(1)
24.576 36.864 See
(2)
See
(2)
See
(2)
See
(2)
(1) This combination of sampling clock frequency and system clock frequency is supported only for the DAC.
(2) This system clock frequency is not supported for the given sampling clock frequency.
SYMBOL PARAMETERS MIN MAX UNIT
t
(SCY)
System clock cycle time 25 ns
t
w(SCH)
System clock high time 0.4 t
(SCY)
ns
t
w(SCL)
System clock low time 0.4 t
(SCY)
ns
System clock duty cycle 40% 60%
Figure 21. System Clock Input Timing
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Product Folder Link(s): PCM3060