Datasheet

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CAT[15:8]: Category Code (DIT)
CLK[29:28]: Clock Accuracy (DIT)
SF[27:24]: Sampling Frequency (DIT)
VALIDL: Validity Bit for L-channel (DIT)
VALIDR: Validity Bit for R-channel (DIT)
SPDIF: S/PDIF Output Control (DIT)
WL[35:32]: Word Length (DIT)
PCM3052A
SLES160 – NOVEMBER 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 78 0 1 0 0 1 1 1 0 CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8
Default value: 0000 0000 (general)
The CAT[15:8] bits control bits[15:8] of channel status bits in compliance with IEC958.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 79 0 1 0 0 1 1 1 1 RSV RSV CLK29 CLK28 SF27 SF26 SF25 SF24
Default value: 00 (level II)
The CLK[29:28] bits control bits[29:28] of channel status bits in compliance with IEC958.
Default value: 0000 (44.1 kHz)
The SF[27:24] bits control bits[27:24] of channel status bits in compliance with IEC958.
B15 B14 B13 B12 B11 B10 B9 B8 • B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 80 0 1 0 1 0 0 0 0 VALIDL VALIDR SPDIF RSV WL35 WL34 WL33 WL32
Default value: 0 (valid)
The VALIDL bit controls the validity bit for L-channel in compliance with IEC958.
Default value: 0 (valid)
The VALIDR bit controls validity bit for R-channel in compliance with IEC958.
Default value: 0
SPDIF = 0 DOUTS disabled (default)
SPDIF = 1 DOUTS enabled
The SPDIF bit controls output from DOUTS pin. In case of default, DOUTS always becomes LOW status.
Default value: 0001 (24 bits)
The WL[35:32] bits control bits[35:32] of channel status bits and the actual data word length of audio sample
word including auxiliary 4-bits from DOUTS pin in compliance with IEC958. If the WL[35:32] bits indicate 16 bits,
the actual data word length of audio sample word is limited to 16 bits even though data input on DIN pin is
24-bits, for example.
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