Datasheet

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BCK
LRCK
DIN
t
(BCH)
t
(BCL)
t
(LRP)
t
(LB)
t
(BCY)
1.4 V
t
(BL)
DOUT
t
(BDO)
t
(LDO)
0.5 V
DD
t
(DIS)
t
(DIH)
1.4 V
1.4 V
T0021−03
PCM3052A
SLES160 – NOVEMBER 2005
PARAMETER MIN MAX UNIT
t
BCY
BCK pulse cycle time 160 ns
t
BCH
BCK pulse duration, HIGH 70 ns
t
BCL
BCK pulse duration, LOW 70 ns
t
BL
BCK rising edge to LRCK edge 20 ns
t
LB
LRCK edge to BCK rising edge 20 ns
t
LRP
LRCK pulse duration 4.2 µ s
t
DIS
DIN setup time to BCK rising edge 20 ns
t
DIH
DIN hold time to BCK rising edge 20 ns
t
BDO
DOUT delay time from BCK falling edge 20 ns
t
LDO
DOUT delay time from LRCK edge 20 ns
t
R
Rising time of all signals 10 ns
t
F
Falling time of all signals 10 ns
NOTE: Load capacitance at DOUT is 20 pF. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing.
Figure 47. Audio Data Input/Output Timing
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