Datasheet

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V
CC
1, V
CC
2,
V
CC
3, V
DD
LRCK, BCK,
SCKI
DOUT
1024 SCKI
Internal Reset
Synchronous Clocks
Power Down Normal Operation
ZERO
PDWN
V
OUT
L, V
OUT
R
(V
CC
1 − V
CC
3 = 5 V,
V
DD
= 3.3 V Typ)
DOUTS
t
(DACDLY1),
2100 /f
S
V
COM
(0.5 V
CC
2)
About 40/f
S
T0098-01
0 V
Synchronous Clocks
0.5 V
CC
2
Normal Operation
t
(DACDLY1),
2100 /f
S
LOW
t
(ADCDLY1)
, 4500 /f
S
PCM3052A
SLES160 – NOVEMBER 2005
Figure 45. DAC Output and ADC Output for External Reset ( PDWN Pin)
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