Datasheet

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V
CC
1, V
DD
0 V
LRCK, BCK,
SCKI
DOUT
1024 SCKI
Internal Reset
Synchronous Clocks
Power Down Normal Operation
ZERO
PDWN
V
OUT
L, V
OUT
R
(V
CC
1 = 5 V,
V
DD
= 3.3 V Typ)
(V
CC
1 = 3.9 V, V
DD
= 2.2 V Typ)
DOUTS
t
(DACDLY1)
, 2100 /f
S
V
COM
(0.5 V
CC
2)
About 40/f
S
t
(ADCDLY1)
, 4500 /f
S
Enable if S/PDIF Bit = HIGHDisable
T0097-01
PCM3052A
SLES160 – NOVEMBER 2005
DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/f
S
following PDWN release.
Notes:
1. Large pop noises can be generated on V
OUT
L and V
OUT
R if the power supply is turned off during normal
operation.
2. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out.
3. Changing mode controls during normal operation can degrade analog performance. It is recommended that
mode controls be changed through the serial control port, and that changing or stopping the clock, switching
the power supply off, etc., be done in the power-down mode.
Figure 44. DAC Output and ADC Output for Power-On Reset
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