Datasheet

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SYSTEM CLOCK
t
w(SCKH)
t
w(SCKL)
2 V
0.8 V
1/256 f
S
T0005−10
System Clock
POWER SUPPLY ON, EXTERNAL RESET, AND POWER DOWN
PCM3052A
SLES160 – NOVEMBER 2005
THEORY OF OPERATION (continued)
The system clock for the PCM3052A must be 256 f
S
, where f
S
is the audio sampling rate, 16 kHz to 96 kHz.
Table 1 lists typical system clock frequencies, and Figure 43 illustrates the system clock timing.
Table 1. Typical System Clock
SAMPLING RATE SYSTEM CLOCK FREQUENCY – MHz
FREQUENCY (f
S
) – LRCK
256 f
S
16 kHz 4.096
32 kHz 8.192
44.1 kHz 11.2896
48 kHz 12.288
96 kHz 24.576
PARAMETER MIN MAX UNIT
t
w(SCKH)
System clock pulse duration, HIGH 16 ns
t
w(SCKL)
System clock pulse duration, LOW 16 ns
Figure 43. System Clock Timing
The PCM3052A has both an internal power-on-reset circuit and an external reset circuit. The sequences for both
resets are shown as follows.
Figure 44 is the timing chart of the internal power-on reset. Two power-on-reset circuits are implemented, one
each for for V
CC
1 and V
DD
. Initialization (reset) is performed automatically at the time when V
CC
1 and V
DD
exceed
3.9 V (typical) and 2.2 V (typical), respectively.
Internal reset is released after 1024 SCKI from power-on-reset release, and the PCM3052A begins normal
operation. V
OUT
L and V
OUT
R from the DAC are forced to the V
COM
(= 0.5 V
CC
2) level as V
CC
2 rises. When
synchronization between SCKI, BCK, and LRCK is maintained, V
OUT
L and V
OUT
R go into the fade-in sequence.
Then V
OUT
L and V
OUT
R provide outputs corresponding to DIN after t
(DACDLY1)
= 2100/f
S
from power-on-reset
release. On the other hand, DOUT from the ADC provides an output corresponding to V
IN
L and V
IN
R after
t
(ADCDLY1)
= 4500/f
S
from power-on-reset release. If synchronization is not maintained, the internal reset is not
released, and operation is kept in the power-down mode. After resynchronization, the DAC goes into the fade-in
sequence, and the ADC goes into normal operation after internal initialization.
DOUTS can provide S/PDIF data after the power-on-reset release if the SPDIF bit is HIGH (see serial control
port for mode control section).
Figure 45 shows timing chart for external reset. The PDWN pin (pin 9) initiates external forced reset when PDWN
= LOW, and it provides the power-down mode, which is the lowest power-dissipation state in the PCM3052A.
When PDWN transitions from HIGH to LOW while SCKI, BCK, and LRCK are synchronized, V
OUT
L and V
OUT
R
are faded out and forced into V
COM
(= 0.5 V
CC
2) level after t
DACDLY1
= 2100/f
S
. At the same time as the internal
reset becomes LOW, DOUT becomes ZERO, the PCM3052A enters the power-down mode. To return to normal
operation, set PDWN to HIGH. Then the power-on reset sequence, Figure 44 , is performed.
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