Datasheet

PCM3010
SLES055 – NOVEMBER 2002
26
www.ti.com
PCM audio interface (continued)
BCK
LRCK
DIN
t
BCH
t
BCL
t
LRP
t
LB
t
BCY
1.4 V
1.4 V
1.4 V
t
BL
DOUT
t
CKDO
t
LRDO
0.5 V
DD
t
DIS
t
DIH
PARAMETER
MIN MAX UNIT
t
BCY
BCK pulse cycle time 80 ns
t
BCH
BCK pulse duration, HIGH 35 ns
t
BCL
BCK pulse duration, LOW 35 ns
t
BL
BCK rising edge to LRCK edge 10 ns
t
LB
LRCK edge to BCK rising edge 10 ns
t
LRP
LRCK pulse duration 2.1 µs
t
DIS
DIN setup time 10 ns
t
DIH
DIN hold time 10 ns
t
CKDO
DOUT delay time from BCK falling edge 20 ns
t
LRDO
DOUT delay time from LRCK edge 20 ns
t
R
Rising time of all signals 10 ns
t
F
Falling time of all signals 10 ns
Figure 49. Audio Data Input/Output Timing
synchronization with digital audio system
The PCM3010 operates with LRCK and BCK synchronized to the system clock. The PCM3010 does not need
a specific phase relationship between LRCK, BCK and the system clock, but does require the synchronization
of LRCK, BCK, and the system clock.
If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due
to LRCK jitter, etc., internal operation of DAC halts within 6/f
S
, and the analog output is forced to 0.5 V
CC
2 until
resynchronization between the system clock, LRCK, and BCK is completed and then t
DACDLY2
elapses.
Internal operation of the ADC also halts within 6/f
S
, and the digital output is forced to a ZERO code until
resynchronization between the system clock, LRCK, and BCK is completed, and then t
ADCDLY2
elapses.
In the case of changes less than ±5 BCKs, resynchronization does not occur and the previously described
discontinuity in analog/digital output control does not occur.