Datasheet

PCM3010
SLES055 – NOVEMBER 2002
22
www.ti.com
system clock (continued)
t
SCKH
System Clock
0.8 V
2.0 V
t
SCKL
1/128 f
S
or 1/192 f
S
1/256 f
S
or 1/384 f
S
1/512 f
S
or 1/768 f
S
PARAMETER
MIN MAX UNIT
t
SCKH
System clock pulse duration HIGH 8 ns
t
SCKL
System clock pulse duration LOW 8 ns
Figure 44. System Clock Timing
power supply on, external reset, and power down
The PCM3010 has both an internal power-on reset circuit and an external reset circuit. The sequences for both
resets are explained as follows.
Figure 45 is the timing diagram for the internal power-on reset. Two power-on reset circuits are implemented
for V
CC
1 and V
DD
, respectively. Initialization (reset) occurs automatically when V
CC
1 and V
DD
exceed 4.0 V and
2.2 V, typically.
Internal reset is released 1024 SCKI clock cycles following the release from power-on reset, and the PCM3010
begins normal operation. V
OUT
L and V
OUT
R from the DAC are forced to the V
COM
(= 0.5 V
CC
2) level as V
CC
2
rises. When synchronization between SCKI, BCK and LRCK is obtained while V
OUT
L and V
OUT
R go into the
fade sequence and provide outputs corresponding to DIN after t
DACDLY1
= 2100/f
S
following release from
power-on reset. On the other hand, DOUT from the ADC provides an output corresponding to V
IN
L and V
IN
R
after t
ADCDLY1
= 4500/f
S
following release from power-on reset. If the synchronization is not held, the internal
reset is not released and device operation remains in the power-down mode. After resynchronization, the DAC
performs the fade-in sequence and the ADC resumes normal operation following internal initialization.
Figure 46 is the external-reset timing diagram. External forced reset, driving the PDWN
pin LOW, puts the
PCM3010 in the power-down mode, which is its lowest power-dissipation state.
When PDWN
transitions from HIGH to LOW while synchronization is maintained between SCKI, BCK, and
LRCK, then V
OUT
L and V
OUT
R are faded out and forced to the V
COM
(= 0.5 V
CC
2) level after t
DACDLY1
= 2100/f
S
.
At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3010 enters into
power-down mode. To enter into normal operation mode again, change PDWN
to HIGH again. The reset
sequence shown in Figure 45 occurs.
Notes:
1. A large popping noise may be generated on V
OUT
L and V
OUT
R when the power supply is turned off during
normal operation.
2. To switch PDWN
during fade in or fade out causes an immediate change between fade in and fade out.
3. To switch the control pins on the fly during normal operation can degrade analog performance. It is
recommended that changing control pins, changing clocks, stopping clocks, turning power supplies off, etc.,
be done in the power-down mode.