Datasheet

PCM3010
SLES055 – NOVEMBER 2002
20
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DAC portion
The DAC portion is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and
a 4th-order noise shaper. This section converts the oversampled input data to the 8-level delta-sigma format.
A block diagram of the 8-level delta-sigma modulator is shown in Figure 41. This 8-level delta-sigma modulator
has the advantage of improved stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 f
S
for
all system clocks. The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown
in Figure 42.
+
+
–
Z
–1
+
++
+
+
+
8-Level Quantizer
–
Z
–1
IN
8 f
S
OUT
64 f
S
+
+
Z
–1
+
+
Z
–1
Figure 41. 8-Level Delta-Sigma Modulator Block Diagram