Datasheet

PCM3010
SLES055 – NOVEMBER 2002
19
www.ti.com
THEORY OF OPERATION
ADC portion
The ADC block consists of a reference circuit, two single-ended to differential converter channels, a fifth-order
delta-sigma modulator with full-differential architecture, a decimation filter with low-cut filter, and a serial
interface circuit which is also used as a serial interface for the DAC input signal as shown in the block diagram,
Figure 1.
The analog front-end diagram illustrates the architecture of the single-ended to differential converter and
antialiasing filter. Figure 40 illustrates the block diagram of the fifth-order delta-sigma modulator and transfer
function.
An on-chip reference circuit with two external capacitors provides all the reference voltages which are needed
in the ADC portion, and defines the full-scale voltage range of both channels.
An on-chip single-ended to differential signal converter saves the design, space, and extra parts cost of an
external signal converter.
Full-differential architecture provides a wide dynamic range and excellent power supply rejection performance.
The input signal is sampled at a ×64 oversampling rate, and an on-chip antialiasing filter eliminates the external
sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using a switched
capacitor technique followed by a comparator, shapes the quantization noise generated by the comparator and
1-bit DAC outside the audio signal band.
The high order delta-sigma modulation randomizes the modulator outputs and reduces the idle tone level.
The 64-f
S
, 1-bit stream from the delta-sigma modulator is converted to a 1-f
S
, 24-bit or 16-bit digital signal by
removing the high-frequency noise components with a decimation filter.
The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed
serial signal through the serial interface, which provides flexible serial formats.
1
st
SW-CAP
Integrator
Analog
In
X(z)
+
–
+
–
2
nd
SW-CAP
Integrator
3
rd
SW-CAP
Integrator
+
–
4
th
SW-CAP
Integrator
+
+
+
+
+
+
+
+
5
th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
Figure 40. Block Diagram of Fifth-Order Delta-Sigma Modulator