Datasheet

PCM3008
SLAS332 – APRIL 2001
7
www.ti.com
theory of operation
ADC section
The PCM3008 ADC consists of a reference circuit, a stereo single-to-differential converter, a stereo fully
differential 5th-order delta-sigma modulator, a digital decimation filter with high pass filter function and a serial
interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section and Figure
1 shows the single-to-differential converter.
An internal reference circuit with one external capacitor provides all reference voltages required by the ADC
and DAC. The internal single-to-differential voltage converter saves the design, space and extra parts needed
for external circuitry required by many delta-sigma converters. The internal full-differential signal processing
architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal
is sampled at 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying
anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators that use a
switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.
The 64f
s
one-bit data stream from the modulator is converted to 1f
s
16-bit data words by the decimation filter,
which also acts as a low pass filter to remove the shaped quantization noise. The dc components are removed
by a high pass filter function contained within the decimation filter.
DAC section
The PCM3008 DAC consists of a serial interface circuit, a 8× digital interpolation filter with de-emphasis filter
function, a stereo 5th-order delta-sigma modulator, and a stereo analog FIR filter with LPF and output buffer
amplifier. The block diagram in this data sheet illustrates the architecture of the DAC section. 1f
s
16-bit audio
data is converted to 8f
s
18-bit data by an 8× oversampling interpolation filter, and then converted to 64f
s
one-bit
data by delta-sigma modulator. One-bit digital data is converted to an analog signal by a current source D to
A, and then high frequency components of the shaped quantization noise out of band is reduced by the analog
FIR filter and LPF. The fade in, fade out function in digital domain, and V
OUT
control circuit in analog domain
provide a pop-noise free muting function that is required for the power down on/off control sequence.
system clock
The system clock for PCM3008 must be either 256f
s
, 384f
s
or 512f
s
, where f
s
is the audio sampling frequency.
The system clock must be supplied on SYSCK (pin 11). PCM3008 also has a system clock detection circuit that
automatically senses 256f
s
, 384f
s
or 512f
s
mode, and when 384f
s
or 512f
s
system clock is used, the clock is
divided into 256f
s
automatically. The 256f
s
clock is used to operate the digital filter and the modulator. The
system clock must be supplied whenever power is applied and either PDAD
or PDDA is HIGH, as the PCM3008
uses dynamic circuits internally. Table 1 lists the relationship of typical sampling frequency and system clock
frequency, and Figure 2 illustrates the system clock timing.
t
SCKL
1/256 f
s
, 1/384 f
s
or 1/512 f
s
0.7 V
CC
0.3 V
CC
t
SCKH
H
L
SYSCK
SYMBOL
DEFINITION MIN UNIT
t
SCKH
System clock pulse width HIGH 15 ns
t
SCKL
System clock pulse width LOW 15 ns
Figure 2. System Clock Timing