Datasheet

PCM3008
SLAS332 – APRIL 2001
10
www.ti.com
PCM audio interface (continued)
0.5 V
CC
0.5 V
CC
0.5 V
CC
0.5 V
CC
t
LRP
t
BCH
t
BCL
t
BL
t
LB
t
BCY
t
DIS
t
DIH
t
BDO
t
LDO
LRCK
BCK
DIN
DOUT
SYMBOL
DEFINITION MIN TYP MAX UNITS
t
BCY
BCK pulse cycle time 300 ns
t
BCH
BCK pulse width high 120 ns
t
BCL
BCK pulse width low 120 ns
t
BL
BCK rising edge to LRCK edge 40 ns
t
LB
LRCK edge to BCK rising edge 40 ns
t
LRP
LRCK pulse width t
BCY
t
DIS
DIN setup time 40 ns
t
DIH
DIN hold time 40 ns
t
BDO
DOUT delay time to BCK falling edge 40 ns
t
LDO
DOUT delay time to LRCK edge 40 ns
t
R
Rising time of all signals 20 ns
t
F
Falling time of all signals 20 ns
Figure 5. Audio Data Input/Output Timing
synchronization with digital audio system
PCM3008 operates with LRCK synchronized to the system clock. PCM3008 does not need a specific phase
relationship between LRCK and system clock, but does require the synchronization of LRCK and system clock.
If the relationship between system clock and LRCK changes more than ±4 BCK during one sample period,
internal operation of DAC halts within 1/f
s
, and analog output is held at the last data until re-synchronization
between system clock and LRCK is completed, and t
DACDLY2
has elapsed.
Internal operation of ADC also halts within 1/f
s
, and digital output is forced into ZERO code until
re-synchronization between system clock and LRCK is completed and t
ADCDLY2
has elapsed. In case of
changes less than ±4 BCK, re-synchronization does not occur and the above analog/digital output control and
discontinuity do not occur. The following figure illustrates the DAC analog output and ADC digital output for loss
of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the
transition of normal to undefined data and undefined data to normal makes a discontinuity of data on analog
and digital output, which also may generate some noise in the audio signal.