Datasheet

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APPLICATION AND LAYOUT CONSIDERATIONS
POWER-SUPPLY BYPASSING
GROUNDING
VOLTAGE INPUT
V
REF
INPUTS
V
COM
INPUT
SYSTEM CLOCK
RST CONTROL
EXTERNAL MUTE CONTROL
TYPICAL CONNECTION DIAGRAM
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
The digital and analog power supply lines to the PCM3006 should be bypassed to the corresponding ground pins
with both 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the device pins as possible. Although the
PCM3006 has three power supply lines to optimize dynamic performance, the use of one common power supply
is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems.
If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems.
In order to optimize the dynamic performance of the PCM3006, the analog and digital grounds are not connected
internally. The PCM3006 performance is optimized with a single ground plane for all returns. It is recommended
to tie all PCM3006 ground pins to the analog ground plane using low-impedance connections. The PCM3006
should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog
ground plane.
A tantalum capacitor, between 1 µ F and 10 µ F, is recommended as an ac-coupling capacitor at the inputs.
Combined with the 30-k Ω characteristic input impedance, a 1- µ F coupling capacitor establishes a 5.3-Hz cutoff
frequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analog
input line. This series resistor, when combined with the 30-k Ω input impedance, creates a voltage divider and
enables larger input ranges.
A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V
REF
1, V
REF
2, and AGND to ensure low source
impedance for the ADC references. These capacitors should be located as close as possible to the reference
pins to reduce dynamic errors on the ADC reference.
A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V
COM
and AGND to ensure low source
impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the
V
COM
pin to reduce dynamic errors on the ADC and DAC common voltage.
The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3006.
The duty cycle and jitter at the system clock input pin should be carefully managed. When power is supplied to
the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must also be supplied simultaneously.
Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipation
and can degrade long-term reliability if the maximum power-dissipation limit is exceeded.
If capacitors larger than 22 µ F are used between V
REF
and V
COM
, external reset control by PDAD = LOW and
PDDA = LOW is required after the V
REF
, V
COM
transient response has settled.
Click noises are caused by dc level changes at the DAC output. To avoid any click noises going in and out of
power-down mode, an external mute control is generally required. The recommended control sequence is as
follows: external mute ON, codec power-down OFF, and then external mute OFF.
NOTE: If SYSCLK is stopped when the PCM3006 is in power-down mode, the device is internally reset.
Figure 39 is a schematic diagram showing typical connections for the PCM3006.
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