Datasheet

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Within 1/f
S
t
(DACDLY2)
(32/f
S
)
Normal Data
V
COM
(0.5 V
CC
)
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DAC V
OUT
State of Synchronization
T0020-03
Normal Data
(1)
Zero DataNormal Data
ADC DOUT
t
(ADCDLY2)
(32/f
S
)
Undefined
Data
OPERATIONAL CONTROL
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 38. DAC Output and ADC Output for Loss of Synchronization
The PCM3006 has hardwire functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control and
DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis.
PDAD: ADC Power-Down Control (Pin 7)
This pin places the ADC section in the lowest power-consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC
power-down-mode enable. Figure 37 illustrates the ADC DOUT response for ADC power-down
ON/OFF. This does not affect the DAC operation.
PDAD POWER DOWN
Low ADC power-down mode enabled
High ADC power-down mode disabled
PDDA: DAC Power-Down Control (Pin 8)
This pin places the DAC section in the lowest power-consumption mode. The DAC operation is
stopped by cutting the supply current to the DAC section and VOUT is fixed to GND during DAC
power-down-mode enable. Figure 37 illustrates the DAC VOUT response for DAC power-down ON/
OFF. This does not affect the ADC operation.
PDDA POWER DOWN
Low DAC power-down mode enabled
High DAC power-down mode disabled
DEM [1:0]: DAC De-Emphasis Control (Pin 17 and Pin 18)
These pins select the de-emphasis mode as shown below:
DEM1 DEM0 DE-EMPHASIS
Low Low De-emphasis 44.1 kHz ON
Low High De-emphasis OFF
High Low De-emphasis 48 kHz ON
High High De-emphasis 32 kHz ON
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