Datasheet

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t
(RST)
Reset Removal
1024 System Clock Periods
PDAD and PDDA
Internal Reset
System Clock
t
(RST)
= 40 ns (min)
Reset
T0015-03
PDAD
= LOW and PDDA = LOW Pulse Duration
T0019-02
Reset Ready/Operation
Internal Reset
or Power Down
DAC V
OUT
t
(DACDLY1)
(16384/f
S
)
Reset Removal or Power Down Off
Power Down
ADC DOUT
Zero Data Normal Data
(1)
V
COM
(0.5 V
CC
)
t
(ADCDLY1)
(18432/f
S
)
Zero Data
GND
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 36. External Forced-Reset Timing
(1) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 37. DAC Output and ADC Output for Reset and Power Down
The PCM3006 operates with LRCIN synchronized to the system clock. The PCM3006 does not require any
specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN
and the system clock. If the relationship between the system clock and LRCIN changes more than 6 bit clocks
(BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC
stops within 1/f
S
, and the analog output is forced to bipolar zero (0.5 V
CC
) until t
(DACDLY2)
delay time after the
system clock is resynchronized to LRCIN. Internal operation of the ADC also stops within 1/f
S
, and the digital
output codes are set to bipolar zero until t
(DACDLY2)
delay time after resynchronization occurs. If LRCIN remains
synchronized to the system clock within 5 or fewer bit clocks, operation is normal. Figure 38 illustrates the effects
on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/f
S
seconds), the
outputs are not defined and some noise may occur. During the transitions between normal data and undefined
states, the output has discontinuities, which cause output noise.
20