Datasheet

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t
(SCKH)
SYSCLK
0.3 V
DD
0.7 V
DD
t
(SCKL)
1/256 f
S
,
1/384 f
S
,
or 1/512 f
S
H
L
T0005-05
RESET
1024 System Clock Periods
Reset Reset Removal
2.4 V
2.2 V
2.0 V
V
DD
Internal Reset
System Clock
T0014-03
3 Clocks Minimum
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
System clock duration, HIGH t
(SCKH)
12 ns (min)
System clock duration, LOW t
(SCKL)
12 ns (min)
Figure 34. System Clock Timing
The PCM3006 has an internal power-on reset circuit, as well as an external forced reset. The internal power-on
reset initializes (resets) when the supply voltage V
DD
> 2.2 V (typ). External forced reset occurs when PDAD =
LOW and PDDA = LOW. Figure 35 shows the internal power-on reset timing and Figure 36 shows the external
forced reset timing by PDAD and PDDA. During external forced reset, the outputs of the DAC are forced to GND
(see Figure 37 ). The analog outputs are then forced to 0.5 V
CC
during t
(DACDLY1)
(16384/f
S
) after reset removal.
The outputs of ADC are also invalid; digital outputs are forced to all zero during t
(ADCDLY1)
(18432/f
S
) after reset
removal.
Figure 35. Internal Power-On Reset Timing
19