Datasheet
www.ti.com
V
REF
2
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
12
V
IN
L
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
BCKIN
DOUT
V
OUT
R
DGND
V
OUT
L
MC/DEM0
MD/DEM1
ZFLG/20BIT
V
DD
DIN
Rch In
Audio
Interface
V
CC
1
24
23
22
21
1
2
3
4
V
CC
1
V
IN
R
V
REF
1
V
CC
2
AGND1
AGND2
V
COM
+
+
0.1 µF
and 10 µF
(1)
MC
(6)
/DEM0
(7)
ZFLG
(6)
/20BIT
(7)
Control
Interface
PCM3002/3003
+
+
1 µF
(3)
4.7 µF
(2)
4.7 µF
(2)
Lch In
+
1 µF
(3)
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
S0014-01
+3 V Analog V
CC
+
+
0.1 µF
and 10 µF
(1)
4.7 µF
(2)
+
4.7 µF
(4)
Rch Out
(5)
Lch Out
(5)
MD
(6)
/DEM1
(7)
0.1 µF
and 10 µF
(1)
ML
(6)
/PDDA
(7)
RST
(6)
/PDAD
(7)
4.7 µF
(4)
10 kΩ
+
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) 0.1- µ F ceramic and 10- µ F tantalum, typical, depending on power supply quality and pattern layout
(2) 4.7- µ F, typical, gives settling time with 30-ms (4.7 µ F × 6.4 k Ω ) time constant in the power ON and power-down OFF
periods.
(3) 1- µ F, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms
(1 µ F × 30 k Ω ) time constant in the power ON and power-down OFF periods.
(4) 4.7- µ F, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with
47-ms (4.7 µ F × 10 k Ω ) time constant in the power ON and power-down OFF periods.
(5) Post low-pass filter with R
IN
> 10 k Ω , depending on system performance requirements
(6) MC, MD, ML, ZFLG, RST, and 10-k Ω pullup resistor are for the PCM3002.
(7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
Figure 51. Typical Connection Diagram for PCM3002/3003
33