Datasheet

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PCM3003 DATA FORMAT CONTROL
Power-Down Control (Pin 7 and Pin 8)
De-Emphasis Control (Pin 17 and Pin 18)
20BIT Audio Data Selection (Pin 16)
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
res: Bit 0: Reserved
This bit is reserved and should be set to 0.
The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control;
DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection.
Both the ADC and DAC power-down control pins place the ADC or DAC section in the lowest
power-consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC
section. DOUT is fixed to zero during ADC power-down mode enable and V
OUT
is fixed to GND during DAC
power-down mode enable. Figure 46 illustrates the ADC and DAC output response for power-down ON/OFF.
PDAD PDDA POWER DOWN
Low Low Reset (ADC/DAC power down enabled)
Low High ADC power-down/DAC operates
High Low ADC operates/DAC power down
High High ADC and DAC normal operation
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins.
DEM1 DEMO DE-EMPHASIS
Low Low De-emphasis enabled for 44.1 kHz
Low High De-emphasis disabled
High Low De-emphasis enabled for 48 kHz
High High De-emphasis enabled for 32 kHz
20BIT FORMAT
Low ADC: 16-bit MSB-first, left-justified
DAC: 16-bit MSB-first, right-justified
High ADC: 20-bit MSB-first, left-justified
DAC: 20-bit MSB-first, right-justified
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