Datasheet

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PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
A[1:0] Bits 10, 9: Register address
These bits define the address for register 2:
A1 A0 REGISTER
1 0 Register 2
PDAD: Bit 8: ADC power-down control
This bit places the ADC section in the lowest power-consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC
power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down
ON/OFF. This does not affect the DAC operation.
PDAD DAC POWER-DOWN STATUS
0 Power-down mode disabled (default)
1 Power-down mode enabled
BYPS: Bit 7: ADC high-pass filter bypass control
This bit enables or disables the high-pass filter for the ADC.
BYPS FILTER BYPASS STATUS
0 High-pass filter enabled (default)
1 High-pass filter disabled (bypassed)
PDDA: Bit 6: DAC power-down control
This bit places the DAC section in the lowest power-consumption mode. The DAC operation is
stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC
power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down
ON/OFF. This does not affect the ADC operation.
PDDA ADC POWER-DOWN STATUS
0 Power-down mode disabled (default)
1 Power-down mode enabled
ATC: Bit 5: DAC attenuation data mode control
When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the
register 1 attenuation data is ignored.
ATC ATTENUATION CONTROL
0 Individual channel attenuation data control (default)
1 Common channel attenuation data control
IZD: Bit 4: DAC infinite zero detection and mute control
This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit
disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously
zero for 65,536 consecutive cycles of BCKIN.
IZD INFINITE ZERO DETECT STATUS
0 Infinite zero detection and mute control disabled (default)
1 Infinite zero detection and mute control enabled
OUT: Bit 3: DAC output enable control
When set to 1, the outputs are forced to V
CC
/2 (bipolar zero). In this case, all registers in the
PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous
programmed state.
OUT DAC OUTPUT STATUS
0 DAC outputs enabled (default normal operation)
1 DAC outputs disabled (forced to BPZ)
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