Datasheet

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MAPPING OF PROGRAM REGISTERS
SOFTWARE CONTROL (PCM3002)
PROGRAM REGISTER 0
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
REGISTER 2 res res res res res A1 A0 PDAD BYPS PDDA ATC IZD OUT DEM1 DEM0 MUT
REGISTER 3 res res res res res A1 A0 res res res LOP res FMT1 FMT0 LRP res
NOTE: res indicates a reserved bit that should be set to 0.
The PCM3002 special functions are controlled using four program registers which are each 16 bits long. There
are four distinct registers, with bits 9 and 10 determining which register is in use. Table 3 describes the functions
of the four registers.
Table 3. Functions of the Registers
REGISTER NAME REGISTER BIT(S) BIT NAME DESCRIPTION
Register 0 15–11 res Reserved, should be set to 0
10–9 A[1:0] Register address 00
8 LDL DAC attenuation data load control for
Lch
7–0 AL[7:0] DAC attenuation data for Lch
Register 1 15–11 res Reserved, should be set to 0
10–9 A[1:0] Register address 01
8 LDR DAC attenuation data load control for
Rch
7–0 AR[7:0] DAC attenuation data for Rch
Register 2 15–11 res Reserved, should be set to 0
10–9 A[1:0] Register address 10
8 PDAD ADC power-down control
7 BYPS ADC high-pass filter bypass control
6 PDDA DAC power-down control
5 ATC DAC attenuation data mode control
4 IZD DAC infinite zero detection and mute
control
3 OUT DAC output enable control
2–1 DEM[1:0] DAC de-emphasis control
0 MUT DAC Lch and Rch soft mute control
Register 3 15–11 res Reserved, should be set to 0
10–9 A[1:0] Register address 11
8–6 res Reserved, should be set to 0
5 LOP ADC/DAC digital loopback control
4 res Reserved, should be set to 0
3–2 FMT[1:0] ADC/DAC audio data format selection
1 LRP ADC/DAC polarity of LR-clock selection
0 res Reserved, should be set to 0
res: Bits 15–11: Reserved
These bits are reserved and should be set to 0.
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