Datasheet

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B8
B15
ML
MC
MD
B9B10B11B12B13B14 B0
B7
B1B2B3B4B5B6
T0023-01
t
(MCH)
ML
LSB
t
(MCL)
t
(MHH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
t
(MLS)
t
(MLL)
t
(MLH)
T0024-02
0.5 V
DD
0.5 V
DD
0.5 V
DD
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 49. Control Data Input Format
MC pulse cycle time t
(MCY)
100 ns (min)
MC pulse duration, LOW t
(MCL)
40 ns (min)
MC pulse duration, HIGH t
(MCH)
40 ns (min)
MD setup time t
(MDS)
40 ns (min)
MD hold time t
(MDH)
40 ns (min)
ML low-level time t
(MLL)
40 ns + 1 SYSCLK
(1)
(min)
ML high-level time t
(MHH)
40 ns + 1 SYSCLK
(1)
(min)
ML setup time
(3)
t
(MLS)
40 ns (min)
ML hold time
(2)
t
(MLH)
40 ns (min)
SYSCLK: 1/256 f
S
or 1/384 f
S
or 1/512 f
S
(1) SYSCLK: System clock cycle
(2) MC rising edge of LSB to ML rising edge
(3) ML rising edge to the next MC rising edge
Figure 50. Control Data Input Timing
26