Datasheet

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T0019-02
Reset Ready/Operation
Internal Reset
or Power Down
DAC V
OUT
t
(DACDLY1)
(16384/f
S
)
Reset Removal or Power Down Off
Power Down
ADC DOUT
Zero Data Normal Data
(1)
V
COM
(0.5 V
CC
)
t
(ADCDLY1)
(18432/f
S
)
Zero Data
GND
EXTERNAL RESET
t
(RST)
Reset Removal
1024 System Clock Periods
RST
or
PDAD and PDDA
Internal Reset
System Clock
t
(RST)
= 40 ns (min)
Reset
T0015-02
RST Pulse Duration
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 46. DAC Output and ADC Output for Reset and Power Down
The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA
(pin 8) for external reset control. As shown in Figure 47 , the external reset signal must drive RST or PDAD and
PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence.
Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles for
completion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence.
Figure 47. External Forced-Reset Timing
The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does not
require any specific phase relationship between LRCIN and the system clock, but there must be synchronization
of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than
6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of
the DAC stops within 1/f
S
, and the analog output is forced to bipolar zero (0.5 V
CC
) until the system clock is
resynchronized to LRCIN followed by t
(DACDLY2)
delay time. Internal operation of the ADC also stops within 1/f
S
,
and the digital output codes are set to bipolar zero until resynchronization occurs followed by t
(ADCDLY2)
delay
time. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48
illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero
(<1/f
S
seconds), the outputs are not defined and some noise may occur. During the transitions between normal
data and undefined states, the output has discontinuities, which cause output noise.
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