Datasheet

www.ti.com
t
(SCKH)
SYSCLK
0.3 V
DD
0.7 V
DD
t
(SCKL)
1/256 f
S
,
1/384 f
S
,
or 1/512 f
S
H
L
T0005-05
POWER-ON RESET
1024 System Clock Periods
Reset Reset Removal
2.4 V
2.2 V
2.0 V
V
DD
Internal Reset
System Clock
T0014-03
3 Clocks Minimum
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 44. System Clock Timing
System clock pulse duration, HIGH t
(SCKH)
12 ns (min)
System clock pulse duration, LOW t
(SCKL)
12 ns (min)
Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the
system clock (SYSCLK) is active and V
DD
> 2.2 V. For the PCM3003, the SYSCLK must complete a minimum of
three complete cycles prior to V
DD
> 2.2 V to ensure proper reset operation. The initialization sequence requires
1024 SYSCLK cycles for completion, as shown in Figure 45 . Figure 46 shows the state of the DAC and ADC
outputs during and after the reset sequence.
Figure 45. Internal Power-On Reset Timing
23