Datasheet

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BCKIN
LRCIN
DIN
t
(BCH)
t
(BCL)
t
(LRP)
t
(LB)
t
(BCY)
0.5 V
DD
t
(BL)
DOUT
t
(BDO)
t
(LDO)
0.5 V
DD
t
(DIS)
t
(DIH)
0.5 V
DD
0.5 V
DD
T0021−01
SYSTEM CLOCK
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN pulse cycle time t
(BCY)
300 ns (min)
BCKIN pulse duration, HIGH t
(BCH)
120 ns (min)
BCKIN pulse duration, LOW t
(BCL)
120 ns (min)
BCKIN rising edge to LRCIN edge t
(BL)
40 ns (min)
LRCIN edge to BCKIN rising edge t
(LB)
40 ns (min)
LRCIN pulse duration t
(LRP)
t
(BCY)
(min)
DIN setup time t
(DIS)
40 ns (min)
DIN hold time t
(DIH)
40 ns (min)
DOUT delay time to BCKIN falling edge t
(BDO)
40 ns (max)
DOUT delay time to LRCIN edge t
(LDO)
40 ns (max)
Rising time of all signals t
(RISE)
20 ns (max)
Falling time of all signals t
(FALL)
20 ns (max)
Figure 43. Audio Data Input/Output Timing
The system clock for the PCM3002/3003 must be either 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the audio sampling
frequency. The system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is
operating at 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divided to 256 f
S
automatically. The 256-f
S
clock is used to operate the digital filters and the delta-sigma modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates
the system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792
48 12.2880 18.4320 24.5760
22