Datasheet

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ML
(1)
20BIT
(2)
Analog
Front-End
Circuit
LRCIN
V
IN
L
Reference
V
REF
1
V
REF
2
V
IN
R
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Decimation
and
High-Pass Filter
Power Supply
Reset and
Power Down
Serial Data
Interface
DOUT
MC
(1)
/DEM0
(2)
V
COM
(+)
(−)
(−)
(+)
Mode
Control
Interface
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
ADC
BCKIN
DIN
Analog
Low-Pass
Filter
V
OUT
L
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
Analog
Low-Pass
Filter
V
OUT
R
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
DAC
MD
(1)
/DEM1
(2)
PDDA
(2)
RST
(1)
/PDAD
(2)
Zero Detect
(1)
Clock
SYSCLK ZFLG
(1)
AGND2 V
CC
2 AGND1 V
CC
1 DGND V
DD
B0004-03
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
BLOCK DIAGRAM
(1) MC, MD, ML, RST, and ZFLG are for PCM3002 only.
(2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.
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